Apple Macintosh Portable Processor-Direct Slot (PPDS) connector pinout

#Computer#Buses and Slots

96 pin Euro-DIN connector pin-out & layout96 pin Euro-DIN connector  at the motherboard

PinName
a1GND
a2+5V
a3+5V
a4+5V
a5/DELAY.CS
a6/VMA
a7/BG
a8/LDS
a9GND
a10A2
a11A5
a12A8
a13A11
a14A14
a15A17
a16reserved
a17n/c
a18reserved
a19reserved
a20D1
a21D4
a22D7
a23D10
a24D13
a25+5/3.7V
a26A19
a27A22
a28FC0
a29/IPL0
a30/BERR
a31GND
a32GND
b1GND
b2+5V
b3+5V
b4+5V
b5/SYS.PWR
b6/BR
b7/DTACK
b8/UDS
b9+5/0V
b10A3
b11A6
b12A9
b13A12
b14A15
b15A18
b16reserved
b17reserved
b18reserved
b19+12V
b20D2
b21D5
b22D8
b23D11
b24D14
b25+5V
b26A20
b27A23
b28FC1
b29/IPL1
b30/EXT.DTACK
b3116M
b32GND
c1GND
c2+5V
c3+5V
c4+5V
c5/VPA
c6/BGACK
c7R/W
c8/AS
c9A1
c10A4
c11A7
c12A10
c13A13
c14A16
c15reserved
c16n/c
c17reserved
c18reserved
c19D0
c20D3
c21D6
c22D9
c23D12
c24D15
c25GND
c26A21
c27E
c28FC2
c29/IPL2
c30/SYS.RST
c31GND
c32GND

D0-D15

Unbuffered data bus, bits 0 through 15

A1-A23

Unbuffered address bus, bits 1 through 23

16M

16 MHz clock

/EXT.DTACK

External data transfer acknowledge. This signal is an input to the processor logic glue. Assertion delays external generation of the /DTACK signal.

E

E(enable) clock

/BERR

Bus error signal generated whenever /AS remains low for more than about 250 us.

/IPL0-/IPL2

Input priority level lines 0 through 2.

/SYS.RST

Initiates a system reset.

/SYS.PWR

A signal from the Power Manager indicated that associated circuits should tri-state their outputs and go inte idle state; /SYS.PWR is pulled high (deasserted) during sleep state.

/AS

Address strobe

/UDS

Upper data strobe

/LDS

Lower data strobe

R/W

Defines bus transfer as read or write signal

/DTACK

Data transfer acknowledge

/DELAY.CS

Indicates that a wait state is inserted into the current memory cycle and that you can delay a CS.

/BG

Bus grant

/BGACK

Bus grant acknowledge

/BR

Bus request

/VMA

Valid memory access

/VPA

Valid peripheral address

FC0-FC2

Function code lines 0 through 2

+5/0V

Provides +5V when the system is running normally and 0V when the system is in sleep mode.

+5/3.7V

Provides +5V when the system is running normally and 3.7V when the system is in sleep mode.

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